One major limitation of modern digital systems is the rate at which data may be transferred from one point to another. This is often complicated by the need for signal-level translation as part of the data interchange. As computer systems have progressed, the need has arisen for a higher and higher speed of data interchange, requiring highly optimized transmitter and receiver designs. For very short distances, high data rates do not pose any significant problem, since the typical signal path is shorter than one-quarter wavelength of the highest frequency of interest in the digital signal. A typical modern computer system uses 5 volt single-ended logic signals conveyed by relatively short signal paths (under one foot in length), with minimal shielding of the signals. When the signal path grows significantly longer, however, or when the data rates become extremely high, then the complex impedance characteristics of the signal path (wires) become significant, and transmission line effects must be taken into account and specialized drivers and receivers must be used. If there is any significant distance between digital components, then there is also the factor of noise problems.
Examples of such high speed data exchange may be found in very high speed computers, in high speed data communications (e.g., EIA RS-422), in high speed disk drive interfaces to personal computers, and in high performance data acquisition systems.
For example, in high speed computing systems, where signal frequencies in excess of 100 MHz may be found, ECL (Emitter Coupled Logic) is often used. ECL signals have very high speed edges which have a great deal of high frequency content. In order to carry these high speed signals about circuit boards reliably, a wiring and termination technique known as "Stripline" is often used. Stripline is a method of routing digital signals on a printed circuit board such that the signal carrying wire is always a fixed distance from (parallel to) a known ground (or "shield"). By carefully controlling the wiring geometry, the characteristic impedance of the signal path is well known. When terminated properly, both transmitter and receiver perceive purely resistive loads, and transmission line reflections are minimized. Noise problems are also reduced, due to the shielding effect of the parallel ground. Although the techniques of ECL could be applied to logic levels as high as 5 volts, an unnecessarily large amount of power would be required and a great deal of radiated noise would be generated. In response to this, ECL logic levels are significantly smaller, having about 2 volts of signal swing.
This technique of carefully controlling the impedance and shielding characteristics of the signal path, and of using relatively low (compared to standard TTL) logic levels to reduce power dissipation is common to most high speed digital data interchange systems.
The typical receiver for a high speed data interchange system comprises a differential comparator followed by a latch. FIG. 1a shows an example of such a "receiver/latch". With respect to FIG. 1a, a receiver/latch 100 comprising a differential comparator 150 and a transparent latch 160 is used to process an incoming data signal "DATA +" applied on a line 110 to the "+" input of the comparator 150. A reference voltage "DATA REF" is applied on a line 140 to the "-" input of the comparator 150. This reference voltage is chosen such that it falls roughly in the middle of the two extremes of the signal excursions of "DATA +", thus giving the best noise immunity. (This assumes that the noise is evenly distributed throughout the input voltage range. If this is not so, then DATA REF would be biased one way or the other, accordingly). A LATCH ENABLE signal 120, indicated here as having a negative logic sense by virtue of an "overbar" in its signal name, is used to "open" latch 160 in its active (logic "0") state, or "close" latch 160 is its inactive (logic "1") state. When latch 160 is "open", the LATCHED DATA output 130 follows the logic level of the output of differential comparator 150. When latch 160 is "closed", LATCHED DATA 130 retains its present value regardless of changes at the input of latch 160.
FIG. 1b shows some of the signal timing relationships for the receiver/latch 100 of FIG. 1a, and uses the same numerical designations. With respect to FIG. 1b, an input data signal 110 is shown where periods of stable or "Valid" data are separated by periods of uncertainty where the signal level is either not known or is in transition from one state to another. Typically such an input signal would be sampled at a point when it is stable. Two cases of sampling signals and resultant output signals are set forth in FIG. 1b to illustrate timing relationships for the receiver/latch. In a first case, (case 1) LATCH ENABLE 120 samples "DATA +" 110 at a time when it is known to be stable. In order for LATCHED DATA 130 to reflect valid data at all times, a minimum setup time t.sub.su is required between the appearance of valid data on "DATA +" 110 and the active portion of the LATCH ENABLE signal. A certain hold time, t.sub.h is also required after the time the LATCH ENABLE signal goes inactive and before the next region of uncertainty in "DATA +". These minimum setup and hold times are due to delays inherent in the differential comparator 150 and the latch 160. For a system of this type, the effective setup time is given by: EQU t.sub.su (overall)=t.sub.d (comparator 150)+t.sub.su (latch 160)
where
t.sub.su (overall) is the overall effective setup time; PA0 t.sub.d (comparator 150) is the signal propagation delay through comparator 150; and PA0 t.sub.su (latch 160) is the minimum setup time for the transparent latch 160. PA0 t.sub.h (overall) is the overall effective hold time; and PA0 t.sub.h (1a t.sub.ch 160) is the minimum hold time for latch 160.
In the case of hold time, the situation is actually improved by the existence of the comparator, since the delay through the comparator effectively reduces the hold time of the latch. This relationship is given by: EQU t.sub.h (overall)=t.sub.h (latch 160)-t.sub.d (comparator 150)
where:
The delay from the LATCH ENABLE signal to LATCHED DATA in FIG. 1b is shown as t.sub.GO.
Case 2 demonstrates the effect of overall propagation delay. In the example of case 2, a wider LATCH ENABLE pulse 120 is applied such that the uncertain period of the input on "DATA +" is reflected in the LATCHED DATA output. The time from when "DATA +" stabilizes to when this stable data is reflected in LATCHED DATA is shown in FIG. 1b gas t.sub.DO, and is equal to the sum of the propagation delays of the input comparator 150 and transparent latch 160.
Because of large delays and setup times, there is also a great o deal of uncertainty about the exact arrival time of valid data at the output of the latch. This is compounded by the possibility of clock skew in many systems, where there is a relative uncertainty between the timing of the signal ("DATA +", in this case) and the timing of the data recovery clock (LATCH ENABLE, in this case). As a result of such uncertainties, the time period during which the "DATA +" signal may be sampled is narrowed considerably, placing limits on overall system speed and performance.
Clearly, the presence of comparator 150 in this configuration has great effect on the data delays, and depending upon how the input data stream is sampled, this may severely limit the maximum data rate of the data exchange system. In response to these problems, design optimization of input and output receivers is now the focus of many major computer companies.